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1 features ? svga resolution, active cmos imager sensor for highest quality images cif-sized sub-sample mode for easy video conferencing stand-alone operation ? need only to supply one 26.6mhz clock ultra-low fixed pattern noise triple 10-bit adcs and column-based cds for highest readout speed high fill factor and sensitivity without microlens distortions full 10-bit data width digital interface for simple, fast transfer easy register-based programming of modes region of interest image scan control for digital zoom and metering on-board color offset and gain control option for full timing and scan control through external fpga direct interface to 8- or 16-bit-based microprocessor bus full power control ? low-power viewfinder mode internal timing mode only covered in this datasheet description the atmel AT76C401 is a complete imager system on one ic that has been designed to give high-quality images using an easy interface and simple operation to reduce overall system cost and time-to-market. the core is a pixel array of 1281 x 480 rectangular active pixels with a high physical fill factor of 43% (without micro-lenses). a vertical stripe rgb pastel color filter is used with individual column-correlated double-sampling (cds) correction circuitry to pro- duce an exceptionally low level of fixed-pattern image noise (fpn). individual color gain and offset controls followed by a triple 10-bit analog-to-digital converter further ensure an even color response in the digitized images. all timing and voltages are generated internally from a single 3.3v voltage rail and master clock, but the option is available to take control of every aspect of scan timing externally in an fpga if the user requires the modes of operation extended for advanced imaging. pre-programmed modes are available for full-resolution still- and motion-imaging with exposures of 1 s to 1 second, as well as for a sub-sampled cif-sized image suitable for the quality and data rates required for video conferencing. region of interest mode additionally allows the user to define on a frame-by-frame basis the area of the imager to be read, enabling easy digital zone or complex multi- spot metering routines utilizing an external fpga. the interface resembles a standard microprocessor bus with a 4-bit address bus and the full image data width of 10 bits operating in a slave mode. when a local processor is not available, the device will stream data in a host mode out to a parallel interface with minimal flow control. dual-mode cmos integrated imager AT76C401 preliminary rev. 1174a ? 03/00 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 2 pin configuration figure 1. AT76C401 pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 48 47 46 45 44 43 24 23 22 21 20 19 25 26 27 28 29 30 agnd nfs nls ack m0 avdd ncs nwr d0 a3 d3 d2 d1 a0 a1 a2 dvdd dgnd row_r nc avdd oag iab iar gs agnd oar oab npx iag d5 d4 nc fr m1 d8 d7 d6 d9 pvdd pgnd row_b nrd mc nc aset test nc top view table 1. pin description pin number id name full name description 1, 48 agnd, avdd analog ground and power supply rail for pixel array and cds block. 2 nfs not frame sync falling edge indicates last row in frame read out. 3 nls not line sync falling edge indicates last pixel in row read out. 4 nc no connect see auxiliary datasheet, ? external timing mode ? . 5 ack acknowledge rising edge signals internal state machines finished last operation. 6, 7 m0, m1 mode 0, mode1 mode control between internal and external timing modes. 8 fr frame reset reset read out counter and pixel array. 9, 31, 39 nc no connect see auxiliary datasheet, ? external timing mode ? . 16, 17 pvdd, pgnd pad v dd and ground digital supply (ac supply). 18 row_b row blanking triggers internal reset and processing of complete row of pixels. 19 gs global set global reset control. returns all registers and counters to default values. 20, 29, 21 iar, iag, iab analog input rgb switchable input to a/d converters (or pin can be left nc). www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 3 27, 22, 28 oar, oag, oab analog output rgb switchable output from gain and offset stage (or pin can be left nc). 24, 25 agnd, avdd analog power and ground supply rail for all analog sections. 26 test vpix test pixel voltage (or pin can be left nc). 23 aset analog set current reference bias via external resistor. 30 npx not pixel clock imager pixel data valid on falling edge. 32 row_r row read triggers the readout of the complete row of pixel data onto the data bus. 33, 34 dgnd, dvdd digital ground and power supply rail for digital core section (dc supply). 35, 36, 37, 38 a0 - a3 address bus register address line. 43, 42, 41, 40, 10, 11, 12, 13, 14, 15 d0 - d9 data bus tristate data bus for read/write to registers and pixel data output. 44 nrd not read falling edge reads addressed register to data bus. 45 nwr not write falling edge writes data bus to addressed register. 46 ncs not chip select chip select for register read/write. data enable during image readout. triggers register to counter transfer on falling edge. 47 mc master clock 26.6mhz (typ) clock. provides synchronous clocking for all digital and data and control. table 1. pin description (continued) pin number id name full name description www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 4 block diagram figure 2. block diagram of AT76C401 analog gain & offset global analog gain column address row address row decoder image sensor array column decoder data address control image sensor logic microcontroller and memory interface logic data port address port control port a-to-d converter analog out analog in analog bias generator image sensor bias generator blue green red bias table 2. physical and electrical parameters parameter measurement units resolution 1281 x 480 or 320 x 120 sub-sampled pixel size 12 x 6 m image area 7.7 x 5.7 mm fill factor 43 % max col fpn 0.2 % dynamic range 57 db power supply 3.3 10% v power consumption 76 mw readout rate 10 mpixels/second frame rate 16 sensitivity (saturation) 20 a/x-sec. conversion gain 1.05 na/e- dark current 0.3 @room temperature na/cm 2 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 5 figure 3. image format noise 130 e- saturation 100 ua peak quantum efficiency 21 % full well capacity 95000 e- programmable gain range 2x - 48x table 2. physical and electrical parameters (continued) parameter measurement units 1 pixel (test) 480 pixels 9 pixels (dark) (0, 0) 21 pixels (dark) e.g. 1281 + 2 pixels 1 pixel (test) (1305, 490) (1304, 0) 6.0um 12um red green blue image sensor array data address control u-controller dram removable memory/ interface data port address port control port image acquisition die betty nwr, nrd, ncs, mc, fr, row_b, row_r, roi, nfs, nls, npx, ack d00 - d09 a00 - a03 avdd agnd dvdd dgnd pvdd pgnd dar, g, b va sa analog aset pix d00 - d15 a00 - a23 nwr, nrd, ncs, mc, fr, row_b, row_r, roi, nfs, nls, npx, ack iar, g, b vdd vss padring vdd vss analog vdd vss digital register value register address 10 4 2 3 3 write read chip select row read row blanking frame reset master clock mode select pixel synch line synch frame synch acknowledge pixel test bias analog trim analog in analog out www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 6 architectural overview active pixel array the pixel used is a three-transistor voltage mode photo- diode design. to initialize the pixel, the reset transistor trst (which is commoned with others across each row) is turned on, and the photodiode active area charges up to the vrst- bias line. when trst is turned off to start the integration, the figure 4. photodiode begins to discharge and the resulting voltage level is buffered by tbuf through to the row select transistor tsel. after integration is complete, transistor tsel (also commoned with other tsel across the row) is turned on, presenting the pixel voltage to the column readout bus. note that the photodiode will continue to integrate if still illu- minated or until it is reset again by activating trst in preparation for another exposure period. see figure 4, figure 5, figure 6 and figure 7. figure 5. figure 6. figure 7. vrstbias trst tsel iload cds circuitry column decoder vout 80ke-/v cpd = 13if spd = 12.3uv/e tbuf integration reset readout sel rst pd vout pd rst vrstbias active sel column iload +ve v 1v 2v .5v 2v .85v .1v 0v www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 7 correlated double sampling a cds block is placed at the bottom of every pixel column bus. using the timing generated from a small state machine (or from an external fpga) the photodiode voltages from all the pixels in a row are applied in parallel to their cds blocks, buffered, clamped and converted to a current. this is then stored in the first of two current memories within each block. cds is then performed by turning on trst, resetting the pixel and storing the reset voltage (after buffering and con- version) in a second current memory. finally, the reset and pixel values are passed out of the cds block (still as a current value) onto one of the three color buses (red, green and blue). if however the cds is turned off by writing to bit 8 of the interface logic register, the operation is reversed with the pixel reading being stored in the second memory location and a reference level equating to a fully saturated pixel written into the first location. the difference of these values, which is passed for a to d conversion, therefore represents an inverse image (note: intensity-inverse rather than color-inverse). when cds is turned off, the pixel is not reset as part of the read cycle, enabling this mode to be used for continu- ous meter during the integration period. figure 8. column signal processor block diagram gain and offset individual gain and offset of output of the three buses is performed using current mode amplifiers under the control of dacs driven by the contents of six registers (5-10) in the analog logic (al) register. a seventh register (11), through a single dac, is used to control three additional amplifiers ganged together to perform global gain. analog access port after gain and offset amplification, the three color buses are made available through ports oar, oag and oab as current signals at a constant voltage for external process- ing as required, being reinserted into ports iar, iag and iab. it is not necessary (or desirable) to link the ports externally if this feature is not used, as the signal can be bridged internally under the control of bits 3 and 4 in the interface logic (inl) register. 10-bit analog to digital converter following the internal or external loopback, the three color bus current signals are passed to three 10-bit, 10 mhz pipelined analog-to-digital converters which require 5 mas- ter clocks for each conversion. to allow settling time on the bus, however, overall each bus is converted at 3.3 mpixels per second. the results of these conversions are available in the ana- log processing (ap) register which is usually presented as full 10-bit width data onto the digital bus under internal or external handshake (see description of operation modes). power control individual control over the main power-consuming blocks are provided in bits 0 to 2 of the interface logic (inl) con- trol register. the bias generators, adc converters and analog amplifiers can be turned off to conserve power in standby. for low power operation, the master clock can also be reduced down to a minimum of 1 mhz. power consumption can further be optimized by reduction of the scan rate under internal control of the rowb and rowr inputs. row/column timing and counters at the core of the scanning circuits are two counters that are incremented to scan across the rows and up the col- umns. under control of bit 9 in the interface logic register, these counters are incremented by one or by four between pixels or rows. the start coordinate of the scan and the block size is writ- ten into the interface sensor logic register by the user over the external bus. this information does not however become active until the control line ncs is strobed high by the user. column of pixels clamp circuit voltage current converter current memory dark current memory signal lout signal lout reset www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 8 the leading edge of ncs causes the start coordinate to be loaded into the internal start register for the main counters and for the end coordinate to be calculated from the start coordinate and the block size, the result being loaded into a second internal stop register. the leading edge of ncs also causes the main counters to be reset to the contents of the internal start register. as the counters are incremented, they are compared with the contents of the internal stop register to determine end of row and frame, triggering a reload to the contents of the internal start register. the user is not required to reload the region of interest registers for every scan of the imager, and anything that is loaded will not become active until ncs is strobed by the user. pulling global set high resets all the registers to their default and automatically triggers this calculation and thus the user is not required to strobe ncs manually. functional description scan control the atmel imager integrates all the functions required to capture, digitize and image. to allow maximum flexibility, the individual functions are register programmable and are accessible from a standard databus. the user can there- fore control precisely the various function blocks to accomplish a customized operation or they can use the four automatic modes of operation most commonly used which are provided by a pre-programmed internal state machine. to use the internally controlled scan modes, only a subset of the total device pins are required and the others should be left unconnected. if the user needs to control the imager completely, an external logic block (possibly in a pld or fpga) needs to be interfaced to the imager utilizing all the device pins. this block will then provide all the timing and control signals to the imager and the internal automatic mode state machines are bypassed. the imager recognizes the two different timing modes by inspection of two control lines and uses an impossible state to force operation to internal timing. pins m0 and m1 (also designated npr and nps in external control mode) have pull down resistors internal and will automatically force the device to internal timing if left unconnected or tied to 0v. only the timing information and pin designations for the internal timing modes are provided in this datasheet. an appendix is available on request containing the full timing diagrams and sample source code from the internal state engine blocks. figure 9. camera system with internal and external timing internal timing generator registers adc cds imager array bypass mux m0 m1 mode1 mode 2 ( ) timing fpga memory and dma i/f data i/o control timing user defined external timing generator and color recovery mode 3, 4, ... x shutter and flash control to system www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 9 internal image scan modes single still frame still operation is achieved using an electronic half shutter and would usually be augmented by an external mechani- cal shutter for high speed exposures. the image sensor logic register is first set to 111111111 and the imager reset by strobing input fr (frame reset) high. the exposure time is determined under external con- trol and can be as short as one ack cycle or as long as the user requires. after the exposure period (and possibly after the external shutter has been closed), the imager is read out on a line- by-line basis starting with the lower left hand corner of the area defined in the image sensor logic (il) register. strob- ing the row blanking (rowb) high causes the imager to process a complete row of image through the cds block (if activated through the msb of interface logic (inl) regis- ter). when this cycle is complete the imager drops ack low and is ready to stream data out. the user then lifts row- read (rowr) high and the imager puts the data on the bus at a maximum rate of one pixel every two master clock (mc) cycles indicating good data on the falling edge of npx. one half master clock cycle after the last falling edge of npx for the last pixel in the row, the imager also drops nls to indicate line sync. strobing rowb again will cause the second row to be read out and so on. after the last line has been read out, the imager also drops nfs low coinci- dent with nls to indicate frame sync. although a mechnical shutter may be used to prevent direct exposure after reading of the image has begun, the pixels will continue to integrate dark current. the readout period once the shutter is closed should therefore be kept as short as possible in relation to the exposure time to avoid a brightness gradient down the picture. if this is not possible due to system or transmission channel constraints, then a simple algorithm can be implemented to correct for it. the next frame exposure is started again by strobing frame reset (fr). www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 10 figure 10. row blanking and row read - exploded view of start pattern gs nfs nls row_r row_b ack npix ncs nwr nrd a<3:0> d(9:0) row blanking 55 mc clocks from ack high to ack low gs register write start of row blanking start of row read (line read) www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 11 full motion for continuous image acquisition, exposure is controlled using a moving blade electronic shutter the width of which is written into the image sensor logic (il) register before a frame is exposed. figure 11. moving blade shutter a single frame is acquired by strobing frame reset (fr) to reset to the top of the frame. fr does not reset the full frame of pixels in this mode. after the reset operation is ack ? d, the user then moves the shutter across the imager by strobing rowb high for each row. this rate should be calculated such that the datastream produced by the imager does not exceed the maximum interface bandwidth and requires to be at a constant rate so that the exposure does not vary across the image. the exposure can be calculated as: the data rate can be calculated as: the exact interface bandwidth will most likely depend heavily upon how the 10-bit data is coded into bytes. users requiring only 8-bit images may opt to drop the 2 lsbs. for the first frame following a frame reset or ncs, valid data is not available until the programmed exposure period for the first line has been reached. during this period, the last n (where n is the number of lines of the exposure) lines of the imager are read out followed by the nfs line going low. as these lines will have been reset at an indeterminate time, the data obtained will be random. to establish the true start of the image, the user should flush the tx buffer following the first frame sync (nfs) and not attempt to count lines as the period will not be constant. the first frame of the image will thus appear to be much shorter/ smaller than the programmed region of interest being the width of the exposure. indeterminate exposure exposure zone number of rows "exposure" in inl register t = "row b strobe period" stop row moving blade shutter *(f = 1/t) reset row n read start row read row n reset reset row wraps to start row before row read reaches stop row *(f = 1/t) * must be identical and constant exposure(ms) row b strobe period no. of rows in register inl = data rate 1 row b strobe period ? () 3 ? x ? block size = www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 12 figure 12. timing diagram showing short first frame subsequent frames of image will contain full valid data as the reset and read points will smoothly wrap around the imager. after the latency determined by the exposure programmed into the exposure register (il), real image data is available at the output. to receive the data, the user strobes rowr after rowb is acknowledged for each row and latches the data on the falling edge of npx. the user must strobe rowr early enough so that the last pixel in the row is out- put before the next rowb strobe is applied to avoid the data being curtailed. however, unless the imager is being run at maximum speed, this is unlikely to pose a problem. gs nfs nls row_r row_b ack npix ncs nwr nrd a<3:0> d(9:0) gs register write start of row blanking start of row read (line read) video mode with 4 x 4 roi and moving blade of 3 lines early nfs www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 13 figure 13. timing diagram showing short first frame (continued) gs nfs nls row_r row_b ack npix ncs nwr nrd a<3:0> d(9:0) video mode with 4 x 4 roi and moving blade of 3 lines early nfs one row blanking and row read, repeats for roi n lines then nfs falls www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 14 figure 14. correct placement of row blanking strobe gs nfs nls row_r row_b ack npix ncs mc nwr nrd a<3:0> d(9:0) start of row blanking www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 15 figure 15. correct placement of row read strobe gs nfs nls row_r row_b ack npix ncs mc nwr nrd a<3:0> d(9:0) start of row read (line read) red pixel green pixel blue pixel www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 16 figure 16. timing showing end of row read gs nfs nls row_r row_b ack npix ncs mc nwr nrd a<3:0> d(9:0) end of row read (line read) and start of next row blanking period red pixel green pixel blue pixel www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 17 figure 17. timing showing end of frame gs nfs nls row_r row_b ack npix ncs mc nwr nrd a<3:0> d(9:0) end of frame red pixel green pixel blue pixel www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 18 region of interest it is possible to define the area of the pixel array the imager scans by writing to register image sensor logic. the lower left hand corner is used as the start address written into the registers as the number of rgb triplets in from the left hand edge and the number of pixel rows up from the bottom. for this calculation, all rows are taken into account, including the black rows (1) and columns (7 rgb triplets). the end position of the scan is set by the user defining the size of the block he wishes to read, writing it as the number of triplets horizontally and the number of rows vertically. if the start point and the size of the block defined would take the scan region over the edge of the pixel array, the imager will scan up to the boundary and then will continue to read out dummy white pixels (fully saturated) up to the specified count when it will stop and raise the appropriate line and field sync lines, continuing with the next row scan at the correct position. the imager will not wrap around onto the beginning of the same or next row. the default value for this register is 0 start point with block size which defines all the 1283 x 481 usable pixels (but it includes the single black pixels on the end/top of the imager). pixels that are not read will not be reset other than through the user strobing frame reset (fr). it is not necessary however as the unread pixels will simply integrate up to saturation and no blooming effect will be visible. figure 18. region of interest ? calculation (0,0) (434,489) (434,0) 0,0 is black pixel 434 pixel "triplets" 489 rows x block size x y block size (a,b) (c,d) c = x start + x block (in triplets) d = y start + y block (in rows) a = il x-start (in triplets) b = il y-start (in rows) a b www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 19 low resolution sub-sample a low-resolution mode that does not require external deci- mation by the user is implemented in the device. the resolution of this mode approximates to a cif resolution and is designed for easy operation of video conferencing or where interface bandwidths are a limiting factor. the low-resolution mode is set by writing the msb of the interface logic (inl) register. this register controls the row and column decode counters to increment by four instead of one so that the resolution is reduced by a factor of 16 to 320 x 120 pixels. one row in every four is read out vertically. similarly, one adjacent rgb triplet is read out and then the next three are skipped. during low resolution mode operation, the start point and block size is still defined in terms of absolute rows and pixel triplets from the bottom left hand corner of the imager. the defaults for the mode are therefore the same as for full resolution. if the region of interest is set at the same time such that the corners of the region do not fall on an even multiple of four, the imager will start scanning at the row and pixel triplet specified and will continue until it is within two rows and two pixel triplets of the specified end point. the user may either calculate this point in advance (setting the registers appro- priately) or may detect the end by inspection of the line sync and field sync outputs. figure 19. sub-resolution mode - pixel pattern non-destructive readout the correlated double sampling mode can be inhibited under control of bit 8 of the interface logic (inl) register. under normal operation, the pixel is reset after every read operation and immediately read again so that fixed offsets can be removed giving the lowest noise possible. when cds is inhibited, the pixel is not reset in between successive reads, allowing scanning of the array during an integration period. to reset the whole pixel array when cds is inhibited, the user must strobe the fr control line (waiting for the ack) if required. note that any image read out when cds is inhibited will be an inverse image as the pixel value is being subtracted from a reference equal to a saturated pixel. the user may thus use this reading for metering purposes with zero being a known maximum exposure. r b g 123 1 23 skip skip 1 2 3 r b g r b g r b g r b g r b g r b g r b g r b g read read read skip skip www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 20 registers table 3. registers block register length external address default value description interface logic (inl) mode register 10 15 (1111) 0 (0000000000) sets mode for analog circuits (i.e. stand-by power & outputs) image sensor logic (il) x-start address y-start address sblock size y block size readout 9 9 9 9 9 0 (0000) 1 (0001) 2 (0010) 3 (0011) 4 (0100) 0 (0000000000) 0 (0000000000) 435 (110110011) 490 (111101010) 490 (111101010) roi horizontal start coordinate roi vertical start coordinate roi horizontal block size roi vertical block size vertical block size for exposure; select readout mode analog logic (al) blue gain blue offset green gain green offset red gain red offset global gain 6 5 6 5 6 5 2 5 (0101) 6 (0110) 7 (0111) 8 (1000) 9 (1001) 10 (1010) 11 (1011) 0 (000000) 0 (00000) 0 (000000) 0 (00000) 0 (000000) 0 (00000) 0 (00) gain for blue channel offset for blue channel gain for green channel offset for green channel gain for red channel offset for red channel overall gain analog processing (ap) data 10 12 (1100) x (xxxxxxxxxx) data output from converter row decoder (rd) test pattern 9 13 (1101) 501 (111110101) test word from row decoder column decoder (cd) test pattern 9 14 (1110) 256 (100000000) test word from column decoder table 4. modes block register length data state interface logic (inl) mode 10 xxxxxxxxx0 xxxxxxxxx1 xxxxxxxx0x xxxxxxxx1x xxxxxxx0xx xxxxxxx1xx xxxxx00xxx xxxxx01xxx xxxxx10xxx xxxxx11xxx xxxx0xxxxx xxxx1xxxxx xx00xxxxxx xx01xxxxxx xx10xxxxxx x0xxxxxxxx x1xxxxxxxx 0xxxxxxxxx 1xxxxxxxxx analog cells on analog cells off a-to-d on a-to-d powered off image sensor bias generator on image sensor bias generator off internal analog signal pathe external analog path between internal analog core & a-to-d core test mode: external connection to internal analog core test mode: external analog path between image sensor array and a-to-d core test mode: encode select pattern in row decoder test mode: encode reset pattern in row decoder normal operation of digital pad drivers test mode #1 for digital pad drivers (nand tree) test mode #2 for digital pad drivers (nand tree) low noise readout non-destructive readout sequential readout sub-sampled readout image sensor logic (il) readout mode 9 111111111 otherwise progressive readout only moving blade readout www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 21 figure 20. timing for loading and reading registers: modes 1 and 2 t sa t ha t scs t hcs t wrw a(0:3) n cs n wr t sa t ha t scs t hcs t rdw t sd t hd t dd t dv d(0:9) in d(0:9) out high z n rd valid address valid address register load register read valid valid high z table 5. timing table symbol characteristic min typ max units t wrw write pulse 18.75 ns t scs setup select device 18.75 ns t sa setup up address 18.75 ns t sd setup up data 18.75 ns t hcs hold select device 18.75 ns t ha hold address 37.5 ns t hd hold data 37.5 ns t rdw read pulse 18.75 ns t dd invalid data period 13.00 ns t scs setup select device 18.75 ns t sa setup up address 18.75 ns t hcs hold select device 18.75 ns t ha hold addrss 37.5 ns t dv valid data 13 ns www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 22 gain and offset values where i out = megadac output current i in = input current g global = global gain g color = gain o color = offset note: 1. these values will be validated when analog cores are fixed. l out 2g global g color l in o color ? = table 6. blue, green & red gain registers (g color ) register value gain 000000 1.00 000001 1.03 000010 1.06 000011 1.09 000100 1.12 ... ... 111110 2.86 111111 2.89 table 7. global gain registers (g global ) register value gain 00 1.0 01 2.0 10 4.0 11 8.0 table 8. blue, green & red offset registers (o color ) register value offset 00000 -2.4 ua (1) 00001 -2.2 ua (1) ... ... 01100 0 ua (1) ... ... 11110 +3.6 ua (1) 11111 +3.8 ua (1) table 9. exposure in continuous mode register value exposure 000000000 1 line 000000000 2 lines ... ... 111101000 489 lines 111101001 490 lines www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 23 color filtering and color recovery the imager utilizes vertical stripes of pastel red, green and blue filtering laid over the pixels which are rectangular with a height to width ratio of 2:1. black and white versions of the imager are available with- out the color filter layers but these still retain the rectangular pixels. to produce full color information for each pixel, the user must perform color recovery externally to the imager, either in hardware or software. when low resolution mode is used, however, it is anticipated that due to the subsampling utilized in the imager, full color recovery would not yield improved image quality. full color information is available vertically and thus color recovery can be achieved simply by processing nine adja- cent pixels sequentially across the row in real time as they are read out of the imager. optimum color recovery is achieved by using a simple median filter transform. this color recovery method is covered under us and international patents (us 4,663,665; 4,774,565 and 4,724,395) but a license to use this algo- rithm will be made available royalty-free to be used only in conjunction with this device. as a working estimate, the color recovery can be per- formed using less than 2000 gates of logic with no additional ram requirements. an appendix to this datasheet giving a full description of the color recovery method is available under nda and a dis- kette containing source code examples of verilog and c- based implementations will be available upon purchase of the imager. the following is a diagram extracted from the patent, outlin- ing the color recovery method. when sub-sampling low-resolution mode is enabled, there is an optical gap of nine pixels between samples which would be incorrectly interpreted by an mft color recovery algorithm as a sharp luminance edge. a preferred color processing algorithm can be provided on request and under nda. due to the design of the imager, pixels are always read out in triplets whatever the size or region of scan set. the color recovery circuit can therefore expect the same rgbrg- brgb sequence within each data stream and that it will start with the red channel. figure 21. filter response characteristic diagram ? color filter transmission in combination with cm500 ir-cutoff table 10. quantum efficiency for pixel of sensor without color filters at 450nm, 550nm, 650nm >20% color filters rgb color stripes (spectral response) optical conversion (including color filters) >40,000 e-/lux-s relative signal (same gain for all channels): broadband filter at 450 nm, 550nm & 650nm matched within 20% triplet order red, green, blue wavelength (nm) normalized response 0 0.5 1 400 500 600 700 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 24 suggested lens information to be supplied. www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 25 packaging information notes: 1. standard quality cover glass: clear glass, ground and polished on both sides, no coatings. 2. occlusion, scratch and dig specification applies only to 9.0 mm by 9.0 mm area centered over the cavity. figure 22. 48-lead clcc package note: for details on plastic packaging, contact your local atmel sales office. figure 23. package marking figure 24. die and sensor location table 11. package and assembly parameter tolerance unit description translation in focal plane 0 60 m displacement in x- and y-direction of image array center protected onto focal plane rotation in focal plane 0 0.25 degree displacement of focal plane centerline axis due to rotation displacement from focal plane 0 25 m displacement perpendicular to focal plane of any part of image sensor arrray cover glass (1) 0.55 0.05 none > 20m 60 - 20 m thickness occlusions (2) scratch and dig (2) (mil-0-13830a) cover glass placement > 2.29 mm distance from front surface of cover glass to focal plane sensor fin g ers deck 1 fin g ers deck 2 0 0 l1 l2 s1 a:left borders pad b:sensor center b a xy a 3893 -11795 b 8345 -6194 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C401 26 specification notes: 1. i dd is with no load on all output. 2. v oh is with i ol = 0.3 ma. 3. v ol low level output voltage is with i ol = 0.3 ma. 4. v ol leakage current with for outputs and bidirectional pads. table 12. absolute maximum ratings symbol parameter min typ max units v dd operating supply voltage -0.3 4.6 v v in dc input voltage -0.3 v dd +0.3 v v out dc output voltage -0.3 v dd +0.3 v temp operating free air temp -40 +85 c table 13. dc operating conditions symbol parameter min typ max units v dd operating supply voltage 3.0 3.3 3.6 v i dd overall supply current 70 ma v ih high level input voltage 0.7 x v dd v dd + 0.3 v v il low level input voltage 0 0.3 x v dd v v oh high level output voltage v dd - 0.1 v v ol low level output voltage v ss + 0.1 v leakage currents 100 na ci load digital input cap load 8 pf co load digital output cap load 43 pf www.datasheet.co.kr datasheet pdf - http://www..net/
? atmel corporation 2000. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard war- ranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel u.k., ltd. coliseum business centre riverside way camberley, surrey gu15 3yl england tel (44) 1276-686-677 fax (44) 1276-686-697 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others. 1174a ? 03/00/0m www.datasheet.co.kr datasheet pdf - http://www..net/

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